Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Timer
Explanation o The PC-9800 main unit has a built-in programmable timer counter
equivalent to the 8253A. It is used for generating interrupt timing for the
interval timer provided by the timer BIOS (INT 1Ch), as a baud rate generator
for RS-232C, etc.
u In the early PC-9800, a discrete 8253A was used, but now it is incorporated
into an ASIC along with other peripheral circuits. In such models, functions
equivalent to the μPD71054, which is upwardly compatible with the 8253A, can be used.
u The PC-98LT-HA and DB-P1 use the V50's built-in TCU (Timer Control Unit).
The V50's built-in TCU is equivalent to the μPD71054.
o The 8253A has three built-in counters that operate independently. The uses
of each counter are as follows:
-------------------------------+----------------+----------------+------------
Model | Counter #0 | Counter #1 | Counter #2
-------------------------------+----------------+----------------+------------
PC-9801 first generation/E/F/M | Interval timer | Memory refresh | RS-232C
-------------------------------+----------------+----------------+------------
PC-98LT/HA | Interval timer | INT 0Ah | RS-232C
-------------------------------+----------------+----------------+------------
DB-P1 | Interval timer | INT 0Ah | Unused
-------------------------------+----------------+----------------+------------
Other models | Interval timer | BEEP frequency | RS-232C
-------------------------------+----------------+----------------+------------
* The RS-232C port of DB-P1 uses the V50HL built-in SCU and is not compatible with PC-98LT/HA.
o The input clock to each counter depends on the system clock frequency.
On the 8253A, counters #0 to #2 can each be input with an independent clock,
but on the PC-9800, the same frequency is input to all.
---------------------+------------------------------
System clock | Counter input clock frequency
---------------------+------------------------------
5M,10MHz series (*1) | 1.9968MHz
8MHz series (*2) | 2.4576MHz
---------------------+------------------------------
*1: When 0000:0501h bit 7=0
*2: When 0000:0501h bit 7=1
o The I/O addresses used by the timer are as follows.
------------+-------+-----+-------------------------------------------------
I/O address | width | R/W | contents
------------+-------+-----+-------------------------------------------------
0071h,3FD9h | BYTE | R/W | Read/write counter #0
0073h,3FDBh | BYTE | R/W | Read/write counter #1
0075h,3FDDh | BYTE | R/W | Read/write counter #2
0077h,3FDFh | BYTE | W | Command write
------------+-------+-----+-------------------------------------------------
* The address 3FDxh is not used in the PC-9801 original/E/F/M, high-resolution
mode, PC-98LT/HA, or DB-P1. It was set up when the use of counter #1 was
changed to beep frequency in PC-9801U/VM2 and later models. When changing the
beep frequency, it is recommended to access it via I/O 3FDBh, to prevent the
memory refresh cycle from being changed on the original PC-9801, E, F, and M.
I/O 0071h,3FD9h
Name Counter #0 Read/Write
Chip 8253A equivalent
Target All PC-9800 series
Function
[READ/WRITE]
bit 7-0: Read/write counter #0
Explanation o Read/write counter #0.
o Counter #0 is used to generate an external interrupt (INT 08h) for the
interval timer. It is used in mode 3 in the BIOS.
u In all models except the PC-9801 original/E/F/M, PC-98LT/HA, DB-P1, and
high-resolution mode, the image is displayed on I/O 3FD9h. However, when
accessing counter #0, it should be accessed via I/O 0071h.
u The interrupt generation frequency when using the interval timer is as follows.
-----------------+------
Model | Frequency
-----------------+------
Other than DB-P1 | 100Hz
DB-P1 | 50Hz
-----------------+------
u PC-98LT/HA, DB-P1 uses the TCU (Timer Control Unit) built into the V50(HL)
as the timer, and the ICU (Interrupt Control Unit) built into the V50(HL) as
the interrupt controller. The I/O addresses of the TCU and ICU are compatible
with normal mode.
u In the case of PC-98HA, DB-P1, the external interrupt that actually occurs
is INT 10h. INT 08h is executed within the INT 10h handler.
Related I/O 0077h
I/O 3FD9h■[PC-9801 original/E/F/M, LT/HA, other than high resolution]
INT 08h
INT 1Ch - Function 02h,03h,04h,05h,06h
I/O 0073h,3FDBh
Name Counter #1 Read/Write
Chip 8253A equivalent
Target All PC-9800 series
Function
[READ/WRITE]
bit 7-0: Read/write counter #1
Explanation o Read/write counter #1.
o In the PC-9801 original/E/F/M, counter #1 is used to generate the memory
refresh rate. Do not change the setting.
o In all models except the PC-9801 original/E/F/M, PC-98LT/HA, and DB-P1, it
is used to set the frequency of the built-in beep. The default frequency is
2kHz. Used in mode 3.
u PC-98LT･HA, DB-P1 use it to generate INT 0Ah interrupt. For details, see
"INT 0Ah (External Interrupt...LT･HA)" in "UNDOCUMENTED 9801/9821 Vol.1".
o PC-9801 original･E･F･M, PC-98LT･HA, DB-P1, and other than high-resolution
mode, the image is displayed on I/O 3FDBh. When setting the frequency of the
built-in beep sound in normal mode, it is recommended to access it from I/O 3FDBh.
u On models equipped with μPD71054, when the beep sound is turned off with I/O
0035h bit 3, the input clock to counter #1 is stopped. This is thought to be
for the purpose of reducing power consumption in notebook computers.
Related I/O 0035h bit 3
I/O 0077h
INT 0Ah (External interrupt...LT･HA)■[PC-98LT･HA,DB-P1]
INT 1Ch - Function 06h■Hi-Res
INT 18h - Function 24h■Hi-Res
I/O 0075h,3FDDh
Name Counter #2 Read/Write
Chip 8253A equivalent
Target All PC-9800 series (except DB-P1)
Function
[READ/WRITE]
bit 7-0: Read/write counter #2
Explanation o Read/write counter #2.
o Counter #2 is used to generate the RS-232C rate. Usually used in mode 3.
o The counter settings corresponding to the transfer speed are as follows.
--------------+-----------------+-------------------+---------------------
Transfer rate | Synchronization | Asynchronous 1/16 | Asynchronous 1/64
(bps) | 5MHz | 8MHz | 5MHz | 8MHz | 5MHz | 8MHz system
--------------+--------+--------+---------+---------+--------+------------
19200 | 128 | N/A | 8 | N/A | N/A | N/A
9600 | 256 | 208 | 16 | 13 | N/A | N/A
4800 | 512 | 416 | 32 | 26 | 8 | N/A
2400 | 1024 | 832 | 64 | 52 | 16 | 13
1200 | 2048 | 1664 | 128 | 104 | 32 | 26
600 | 4096 | 3328 | 256 | 208 | 64 | 52
300 | 8192 | 6656 | 512 | 416 | 128 | 104
150 | 16384 | 13312 | 1024 | 832 | 256 | 208
75 | 32768 | 26624 | 2048 | 1664 | 512 | 416
--------------+--------+--------+---------+---------+--------+------------
u For devices that do not support 19200bps, the guaranteed transfer speed is
up to 9600bps. To determine whether or not the machine is 19200bps compatible, refer to
F8E8:0002h (normal) and FFE8:0002h (high-resolution).
u In fact, even if the machine is not 19200bps compatible, it is possible to
communicate at speeds of 9600bps or more by directly operating this I/O port.
u In PC-9801 original/E/F/M, PC-98LT/HA, DB-P1, and other modes other than
high-resolution mode, the image is displayed on I/O 3FDDh. However, when
accessing counter #2, access should be made via I/O 0075h.
Related I/O 0434h■[19200bps compatible machine]
I/O 0077h
F8E8:0002h bit 2■[Normal]
FFE8:0002h bit 2■[High-resolution]
INT 19h - Function 00h(BIOS)
I/O 0077h,3FDFh
Name Mode setting
Chip 8253A equivalent
Target All PC-9800 series
Function
[READ] None
[WRITE] Mode specification
bit 7,6: SC1,SC0 - Select counter
11b = Multiple latch command■[Only for models with μPD71054]
10b = Counter #2
01b = Counter #1
00b = Counter #0
■[Other than multiple latch command]
bit 5,4: RL1,RL0 - Read/write
11b = Read/write in the order of LSB,MSB
10b = Read/write MSB
01b = Read/write LSB
00b = Count latch command
bit 3〜1: M2〜M0 - Mode
101b = Mode 5 (hardware triggered strobe) (*)
100b = Mode 4 (software triggered strobe)
x11b = Mode 3 (square wave generator)
x10b = Mode 2 (rate generator)
001b = Mode 1 (gate terminal retriggerable one shot) (*)
000b = Mode 0 (interrupt at end of count)
(*) On the PC-9800, the GATE terminal of the 8253A is unchanged (pulled up),
so modes 1 and 5 cannot be used effectively.
bit 0: BCD
1 = BCD count
0 = Binary count
■[Multiple latch command]
bit 5: COUNT#
1 = Do not latch counter
0 = Latch counter
bit 4: STATUS#
1 = Do not latch status
0 = Latch status
bit 3: CNT2
bit 2: CNT1
bit 1: CNT0
1 = Select
0 = Do not select
bit 0: Unused (always 0)
Explanation o Sets the timer mode.
o Before reading/writing counters #0 to #2, the mode must be set in advance.
u On the PC-9800, the GATE terminal of the 8253A is unchanged (pulled up), so
mode 1 and mode 5 cannot be used effectively.
u In PC-9801 original/E/F/M, PC-98LT/HA, DB-P1, and other than high-resolution
mode, the image is displayed on I/O 3FDFh.
u Multiple latch commands can be used on machines equipped with μPD71054.
However, there is no way to determine whether or not the machine is equipped with μPD71054.
Related I/O 0071h
I/O 0073h
I/O 0075h